View ADP5033_820352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs ADP5033
FEATURES
Main input voltage range: 2.3 V to 5.5 V Two 800 mA buck regulators and two 300 mA LDOs Tiny, 16-ball, 2 mm x 2 mm WLCSP package Regulator accuracy: 3% Factory programmable VOUTx 3 MHz buck operation with forced PWM and auto PWM/PSM modes BUCK1/BUCK2: output voltage range from 0.8 V to 3.3 V LDO1/LDO2: output voltage range from 0.8 V to 3.3V LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V LDO1/LDO2: high PSRR and low output noise
The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in P M . When around the nominal value and the load current falls predefined threshold, the regulator operates in improving the light load efficiency. The two bucks operate out of phase to reduce the input capacitor requirement and noise. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5033 LDO extend the battery life of portable devices. The ADP5033 LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. The regulators in the ADP5033 are activated by the ENA and ENB pins. The specific channels controlled by ENA and ENB are set by factory programming. A high voltage level applied to the enable pins activates the regulators. The default output voltages are factory programmable and can be set to a wide range of options.
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices
GENERAL DESCRIPTION
The ADP5033 combines two high performance buck regulators and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm x 2 mm WLCSP to meet demanding performance and board space requirements.
TYPICAL APPLICATION CIRCUIT
ADP5033
2.3V TO 5.5V VIN1 C1 4.7F ENA ON OFF ENB SW1 VOUT1 L1 1H C5 10F VOUT1 @ 800mA
BUCK1
ACTIV. AND UVLO
EN1 MODE EN2 EN3 EN4 MODE
PGND1
MODE L2 1H
PWM PSM/PWM
VIN2 C2 4.7F
EN2
SW2 VOUT2
VOUT2 @ 800mA C6 10F
BUCK2
PGND2
1.7V TO 5.5V
VIN3 C3 1F VIN4 C4 1F
EN3
(ANALOG)
LDO1
VOUT3 C7 1F
VOUT3 @ 300mA
EN4
(DIGITAL)
LDO2
VOUT4 C8 1F
VOUT4 @ 300mA
09788-001
AGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011 Analog Devices, Inc. All rights reserved.
ADP5033 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 General Specifications ................................................................. 3 BUCK1 and BUCK2 Specifications ........................................... 4 LDO1 and LDO2 Specifications................................................. 4 Input and Output Capacitor, Recommended Specifications.. 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Power Dissipation and Thermal Considerations ....................... 15 Buck Regulator Power Dissipation .......................................... 15 Junction Temperature ................................................................ 16 Theory of Operation ...................................................................... 17 Power Management Unit........................................................... 17 BUCK1 and BUCK2 .................................................................. 18 LDO1 and LDO2........................................................................ 19 Applications Information .............................................................. 20 Buck External Component Selection....................................... 20 LDO Capacitor Selection .......................................................... 22 PCB Layout Guidelines.................................................................. 23 Typical Application Schematic ..................................................... 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
5/11--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADP5033 SPECIFICATIONS
GENERAL SPECIFICATIONS
VIN1 = VIN2 = VIN3 = VIN4 = 2.3 V to 5.5 V; VIN3 = VIN4 = 1.7 V to 5.5 V; TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 1.
Parameter INPUT VOLTAGE RANGE THERMAL SHUTDOWN Threshold Hysteresis START-UP TIME 1 BUCK1, LDO1, LDO2 BUCK2 ENA, ENB, MODE INPUTS Input Logic High Input Logic Low Input Leakage Current STANDBY CURRENT All Channels Enabled All Channels Disabled VIN1 UNDERVOLTAGE LOCKOUT High UVLO Input Voltage Rising High UVLO Input Voltage Falling Low UVLO Input Voltage Rising Low UVLO Input Voltage Falling
1
Symbol VIN1, VIN2 TSSD TSSD-HYS tSTART1 tSTART2 VIH VIL VI-LEAKAGE ISTBY-NOSW ISHUTDOWN UVLOVIN1RISE UVLOVIN1FALL UVLOVIN1RISE UVLOVIN1FALL
Test Conditions/Comments
Min 2.3
Typ
Max 5.5
Unit V C C s s V V A A A V V V V
TJ rising
150 20 250 300 1.1 0.05 0.4 1 175 1 3.9 3.1 2.275 1.95
No load, no buck switching TJ = -40C to +85C
108 0.3
Start-up time is defined as the time from VIN1 > UVLOVIN1RISE to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal levels.
Rev. 0 | Page 3 of 28
ADP5033
BUCK1 AND BUCK2 SPECIFICATIONS
VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted.1 Table 2.
Parameter INPUT CHARACTERISTICS Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Accuracy
Symbol
VIN1, VIN2 VOUT1, VOUT2 VOUT1, VOUT2 IOUT1, IOUT2 IPSM IIN IIN IIN RPFET RPFET RNFET RNFET ILIMIT1, ILIMIT2 RPDWN-B fSW
Test Conditions/Comments
Min 2.3 -3
Typ
Max 5.5 +3
Unit V %
PWM mode, ILOAD1 = ILOAD2 = 0 mA to 800 mA
PWM mode; VIN1 = VIN2 = 2.3 V to 5.5 V; ILOAD1 = ILOAD2 = 0 mA to 800 mA
Line Regulation Load Regulation
PSM CURRENT THRESHOLD PSM to PWM Operation OPERATING SUPPLY CURRENT BUCK1 Only BUCK2 Only BUCK1 and BUCK2 SW CHARACTERISTICS SW On Resistance
PWM mode ILOAD = 0 mA to 800mA, PWM mode
-0.05 -0.1 100
%/V %/A
mA A A A 235 295 190 220 m m m m mA MHz
MODE = ground ILOAD1 = 0 mA, device not switching, all other channels disabled. ILOAD2 = 0 mA, device not switching, all other channels disabled. ILOAD1 = ILOAD2 = 0 mA, device not switching, LDO channels disabled. pFET at VIN1 = 5 V pFET at VIN1 = 3.6 V nFET at VIN1 = 5 V nFET at VIN1 = 3.6 V pFET switch peak current limit
44 55 67 145 180 110 125 1350 75 3.0
Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY
1
1100 2.5
Channel disabled
3.5
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO1 AND LDO2 SPECIFICATIONS
VIN3 = (VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, VIN4 = (VOUT4 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT = 1 F; TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted.1 Table 3.
Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Bias Current per LDO2 Symbol VIN3, VIN4 IVIN3BIAS/IVIN4BIAS Test Conditions/Comments Min 1.7 Typ Max 5.5 30 100 245 Unit V A A A A A +3 +0.03 0.001 65 85 165 600 600 0.003 110 % %/ V %/mA mV mV mV mA
Total System Input Current LDO1 or LDO2 Only LDO1 and LDO2 Only OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation3 DROPOUT VOLTAGE4
IIN
IOUT3 = IOUT4 = 0 A IOUT3 = IOUT4 = 10 mA IOUT3 = IOUT4 = 300 mA Includes all current into VIN1, VIN2, VIN3, and VIN4 IOUT3 = IOUT4 = 0 A, all other channels disabled IOUT3 = IOUT4 = 0 A, buck channels disabled 100 A < IOUT3 < 300 mA, 100 A < IOUT4 < 300 mA; VIN3 = (VOUT3 + 0.5 V) to 5.5 V, VIN4 = (VOUT4 + 0.5 V) to 5.5 V VIN3 = (VOUT3 + 0.5 V) to 5.5 V, VIN4 = (VOUT4 + 0.5 V) to 5.5 V, IOUT3 = IOUT4 = 1 mA IOUT3 = IOUT4 = 1 mA to 300 mA VOUT3 = VOUT4 = 3.3 V VOUT3 = VOUT4 = 2.5 V VOUT3 = VOUT4 = 1.8 V 335 Channel disabled
Rev. 0 | Page 4 of 28
10 60 165 53 74 -3 -0.03
VOUT3, VOUT4 VOUT3/VIN3, VOUT4/VIN4 VOUT3/IOUT3, VOUT4/IOUT4 VDROPOUT
CURRENT-LIMIT THRESHOLD5 ACTIVE PULL-DOWN
ILIMIT3, ILIMIT4 RPDWN-L
ADP5033
Parameter POWER SUPPLY REJECTION RATIO Regulator LDO1 Symbol PSRR Test Conditions/Comments Min Typ Max Unit
Regulator LDO2
10 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 10 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 100 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 1 MHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA
60 62 63 54 57 64
dB dB dB dB dB dB
1 2
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).2 This is the input current into VIN3/VIN4, which is not delivered to the output load. 3 Based on an endpoint calculation using 1 mA and 100 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = -40C to +125C, unless otherwise specified. Table 4.
Parameter SUGGESTED INPUT AND OUTPUT CAPACITANCE BUCK1, BUCK2 Input Capacitor BUCK1, BUCK2 Output Capacitor LDO1, LDO2 1 Input and Output Capacitors CAPACITOR ESR
1
Symbol CMIN1, CMIN2 CMIN1, CMIN2 CMIN3, CMIN4 RESR
Min 4.7 10 0.70 0.001
Typ
Max 40 40 1
Unit F F F
The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs.
Rev. 0 | Page 5 of 28
ADP5033 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter VIN1, VIN2, VIN3, VIN4, VOUT1, VOUT2, VOUT3, VOUT4, ENA, MODE, ENB to Ground Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model Rating -0.3 V to +6 V
THERMAL RESISTANCE
JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance
-65C to +150C -40C to +125C JEDEC J-STD-020 1500 V 500 V 100 V Package Type 16-Ball, 0.5 mm Pitch WLCSP JA 57 JB 14 Unit C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For detailed information on power dissipation, see the Power Dissipation and Thermal Considerations section.
Rev. 0 | Page 6 of 28
ADP5033 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1 INDICATOR 1 A AGND MODE B VIN1 C PGND1 SW1 D
09788-002
2
3
4
VOUT3 VIN3
VIN4 VOUT4
ENA
ENB
VOUT1 VOUT2 VIN2
SW2
PGND2
TOP VIEW (BALL SIDE DOWN) Not to Scale
Figure 2. Pin Configuration--View from the Top of the Die
Table 7. Pin Function Descriptions
Pin No. A1 A2 A3 A3 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 Mnemonic VOUT3 VIN3 VIN4 VOUT4 AGND MODE ENA ENB VIN1 VOUT1 VOUT2 VIN2 PGND1 SW1 SW2 PGND2 Description LDO1 Output Voltage and Sensing Input. LDO1 Input Supply (1.7 V to 5.5 V, VIN4 VIN1 = VIN2). LDO2 Input Supply (1.7 V to 5.5 V, VIN3 VIN1 = VIN2). LDO2 Output Voltage and Sensing Input. Analog Ground. BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. Regulator Enable Pin A, Active High. The regulators turned on with ENA are factory programmed. Regulator Enable Pin B, Active High. The regulators turned on with ENB are factory programmed. BUCK1 Input Supply (2.3 V to 5.5 V) and UVLO Detection. Connect VIN1 to VIN2. BUCK1 Output Voltage Sensing Input. BUCK2 Output Voltage Sensing Input. BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1. Dedicated Power Ground for BUCK1. BUCK1 Switching Node. BUCK2 Switching Node. Dedicated Power Ground for BUCK2.
Rev. 0 | Page 7 of 28
ADP5033 TYPICAL PERFORMANCE CHARACTERISTICS
VIN1= VIN2 = VIN3= VIN4 = 5.0 V, TA = 25C, unless otherwise noted.
140 120 100 80 60 40
3.35
VIN = 4.2V, +85C VIN = 4.2V, +25C VIN = 4.2V, -40C
QUIESCENT CURRENT (A)
3.33
VOUTA (V)
09788-139
3.31
3.29
3.27
20 0 2.3
2.8
3.3
3.8
4.3
4.8
5.3
0
0.1
0.2
0.3
INPUT VOLTAGE (V)
0.4 IOUT (A)
0.5
0.6
0.7
0.8
Figure 3. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.2 V, VOUT4 = 3.3 V, All Channels Unloaded
T
Figure 6. BUCK1 Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode
1.864
SW
4 2
1.844
VIN = 3.6V, +85C VIN = 3.6V, +25C VIN = 3.6V, -40C
VOUT
VOUTA (V)
1.824
1
EN IIN
1.804
1.784
3
09788-021
0
0.1
0.2
0.3
T 11.20%
0.4 0.5 IOUT (A)
0.6
0.7
0.8
Figure 4. Buck1 Startup, VOUT1 = 3.3 V, IOUT1 = 10 mA
Figure 7. BUCK2 Load Regulation Across Temperature, VOUT2 = 1.8 V, Auto Mode
0.799 0.798 VIN = 3.6V, +85C VIN = 3.6V, +25C VIN = 3.6V, -40C
T
SW
4 2
0.797 0.796
VOUT
VOUTA (V)
0.795 0.794 0.793 0.792 0.791
1
EN IIN
3
0.790
09788-020
0
0.1
0.2
0.3
T 11.20%
0.4 0.5 IOUT (A)
0.6
0.7
0.8
Figure 5. BUCK2 Startup, VOUT2 = 1.8 V, IOUT2 = 5 mA
Figure 8. BUCK1 Load Regulation Across Input Voltage, VOUT1 = 3.3 V, PWM Mode
Rev. 0 | Page 8 of 28
09788-054
CH1 2.00V CH3 5.00V
CH2 50.0mA CH4 5.00V
M 40.0s
A CH3
2.2V
0.789
09788-057
CH1 2.00V CH3 5.00V
CH2 50.0mA CH4 5.00V
M 40.0s
A CH3
2.2V
1.764
09788-058
3.25
ADP5033
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 IOUT (A) 0.1 VIN = 3.9V VIN = 4.2V VIN = 5.5V
09788-038
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 1 0 0.001 0.01 IOUT (A) 0.1 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 1
09788-035
Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode
100 90 80 70 EFFICIENCY (%)
Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode
100 90 80 70
EFFICIENCY (%)
60 50 40 30 20 10 0 0.001 0.01 IOUT (A) 0.1 VIN = 3.9V VIN = 4.2V VIN = 5.5V
09788-039
60 50 40 30 20 10 VIN = 2.3V VIN = 3.6V VIN = 4.2V VIN = 5.5V 0.01 IOUT (A) 0.1 1
09788-034
1
0 0.001
Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode
100 90 80 70
EFFICIENCY (%)
Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, Auto Mode
100 90 80 70
EFFICIENCY (%)
60 50 40 30 20 10 0 0.001 0.01 IOUT (A) 0.1 VIN = 2.3V VIN = 3.6V VIN = 4.2V VIN = 5.5V
09788-036
60 50 40 30 20 10 VIN = 2.3V VIN = 3.6V VIN = 4.2V VIN = 5.5V 0.01 IOUT (A) 0.1 1
09788-065
1
0 0.001
Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, Auto Mode
Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, PWM Mode
Rev. 0 | Page 9 of 28
ADP5033
100 90 80
3.3 3.2 3.1
FREQUENCY (MHz)
70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.001 0.01 IOUT (A) 0.1 +25C +85C -40C
09788-062
3.0 2.9 2.8 2.7 2.6 2.5 TA = +25C TA = -40C TA = +85C 0 0.2 0.4 0.6 IOUT (A) 0.8 1.0 1.2
09788-040
1
Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V, Auto Mode
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.001 0.01 IOUT (A) 0.1 +85C +25C -40C 1
09788-063
Figure 18. BUCK2 Switching Frequency vs. Output Current, Across Temperature, VOUT2 = 1.8 V, PWM Mode
T VOUT
1
ISW
2
SW
4
09788-025 09788-024
CH1 50.0V
CH2 500mA CH4 2.00V
M 4.00s T 28.40%
A CH2
240mA
Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature, VOUT2 = 1.8 V, Auto Mode
100 90 80 70
EFFICIENCY (%)
Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
T VOUT
1
60 50 40 30 20 10 0 0.001 0.01 IOUT (A) 0.1 +85C +25C -40C 1
09788-200
ISW
2
SW
4
CH1 50.0V
CH2 500mA CH4 2.00V
M 4.00s T 28.40%
A CH2
220mA
Figure 17. BUCK2 Efficiency vs. Load Current, Across Temperature,
Figure 20. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Auto Mode
Rev. 0 | Page 10 of 28
ADP5033
T VOUT
1
T
VIN ISW
VOUT
1
2
SW
SW
4 3 4
09788-027 09788-013 09788-015
CH1 50mV
CH2 500mA CH4 2.00V
M 400ns T 28.40%
A CH2
220mA
CH1 50.0mV CH3 1.00V
CH4 2.00V
M 1.00ms T 30.40%
A CH3
4.80V
Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
Figure 24. BUCK2 Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode
T SW
4
T VOUT
1
ISW
2
VOUT
1
SW
IOUT
4
09788-026
2
09788-016
CH1 50mV
CH2 500mA CH4 2.00V
M 400ns T 28.40%
A CH2
220mA
CH1 50.0mV
CH2 50.0mA CH4 5.00V
M 20.0s A CH2 T 60.000s
356mA
Figure 22. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode
Figure 25. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Auto Mode
T
SW
T
VIN
4
VOUT
1
1
VOUT
SW
IOUT
3
2
CH4 2.00V
T 30.40%
09788-012
CH1 50.0mV CH3 1.00V
M 1.00ms
A CH3
4.80V
CH1 50.0mV
CH2 50.0mA CH4 5.00V
M 20.0s A CH2 T 22.20%
379mA
Figure 23. Buck1 Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode
Figure 26. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA, VOUT2 = 1.8 V, Auto Mode
Rev. 0 | Page 11 of 28
ADP5033
T SW T
4 2
IIN
VOUT
1
VOUT
1
IOUT
EN
2
3
09788-017
T 20.40%
T 11.20%
Figure 27. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, VOUT1 = 3.3 V, Auto Mode
T SW
4
Figure 30. LDO Startup, VOUT3 = 3.0 V, IOUT3 = 5 mA
2.820 2.815 2.810 2.805
VOUT
VIN = 3.3V VIN = 4.5V VIN = 5.0V VIN = 5.5V
1
VOUTC (V)
2.800 2.795 2.790 2.785
IOUT
2
09788-018
0
0.05
0.10
T 19.20%
0.15 IOUT (A)
0.20
0.25
0.30
Figure 28. BUCK2 Response to Load Transient, IOUT2 from 20 mA to 180 mA, VOUT2 = 1.8 V, Auto Mode
Figure 31. LDO Load Regulation Across Input Voltage, VOUT3 = 2.8 V
T VOUT2
2
3.45
3.40
VIN = 4.2V, +85C VIN = 4.2V, +25C VIN = 4.2V, -40C
SW1
3.35
VOUTD (V)
3
3.30
VOUT1
1
3.25
SW2
3.20
4
09788-066
0
0.05
0.10
T 50.00%
0.15 IOUT (A)
0.20
0.25
0.30
Figure 29. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode Showing Out-of-Phase Operation
Figure 32. LDO Load Regulation Across Temperature, VIN3 = 3.3 V, VOUT3 = 2.8 V
Rev. 0 | Page 12 of 28
09788-049
CH1 5.00V CH3 5.00V
CH2 5.00V CH4 5.00V
M 400ns
A CH4
1.90V
3.15
09788-046
CH1 100mV
CH2 200mA CH4 5.00V
M 20.0s A CH2
88.0mA
2.780
09788-022
CH1 50.0mV
CH2 200mA CH4 5.00V
M 20.0s A CH2
408mA
CH1 2.00V CH3 5.00V
CH2 50.0mA
M 40.0s
A CH3
2.2V
ADP5033
3.0
T
2.5
VIN
2.0
VOUTC (V)
1.5
1 2
VOUT
1.0
0.5
09788-045
T 28.40%
Figure 33. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V
Figure 36. LDO Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT3 = 2.8 V
60 5VIN 55 3.3VIN 50
50 45 40
GROUND CURRENT (A)
35 30 25 20 15 10 5 0 0.05 0.10 0.15 0.20 0.25
09788-136
RMS NOISE (V)
45
40 35 30 25 0.001
0.01
0.1
LOAD CURRENT (A)
1 ILOAD (mA)
10
100
Figure 34. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
Figure 37. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 2.8 V
65 60 5VIN 3.3VIN
T
IOUT
2
55
RMS NOISE (V)
50 45 40 35 30
1
VOUT
09788-019
0.01
0.1
T 19.20%
1 ILOAD (mA)
10
100
Figure 35. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA, VOUT3 = 2.8 V
Figure 38. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 3.0 V
Rev. 0 | Page 13 of 28
09788-048
CH1 100mV
CH2 100mA
M 40.0s A CH2
52.0mA
25 0.001
09788-047
0
09788-014
0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 VIN (V)
IOUT = 300mA IOUT = 150mA IOUT = 100mA IOUT = 10mA IOUT = 1mA IOUT = 100A
3
CH1 20.0mV CH3 1.00V
M 100s
A CH3
4.80V
ADP5033
0 -10 -20 -30
PSRR (dB)
0 100A 1mA 10mA 50mA 100mA 150mA
PSRR (dB)
-20
-40
100A 1mA 10mA 50mA 100mA 150mA
-40 -50 -60 -70 -80 -90
09788-050
-60
-80
-100
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 39. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
0
Figure 41. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V
0 -10 100A 1mA 10mA 50mA 100mA 150mA
-20
-20 -30
PSRR (dB)
-40
PSRR (dB)
-40 -50 -60 -70 -80 -90
-60
-80
-100
09788-051
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 40. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V
Figure 42. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V
Rev. 0 | Page 14 of 28
09788-052
-120 10
100A 1mA 10mA 50mA 100mA 150mA
-100 10
09788-053
-100 10
-120 10
ADP5033 POWER DISSIPATION AND THERMAL CONSIDERATIONS
The ADP5033 is a highly efficient micropower management unit (PMU), and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (125C). When the temperature exceeds 150C, the ADP5033 turns off all the regulators, allowing the device to cool down. When the die temperature falls below 130C, the ADP5033 resumes normal operation. This section provides guidelines to calculate the power dissipated in the device and ensure that the ADP5033 operates below the maximum allowable junction temperature. The efficiency for each regulator on the ADP5033 is given by
BUCK REGULATOR POWER DISSIPATION
The power loss of the buck regulator is approximated by
PLOSS = PDBUCK1 + PDBUCK2 + PL
(3)
where: PDBUCK is the power dissipation on one of the ADP5033 buck regulators. PL is the inductor power losses. The inductor losses are external to the device, and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by
PL IOUT1(RMS)2 x DCRL
(4)
=
POUT x 100% PIN
(1)
where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator.
where: is the efficiency. PIN is the input power. POUT is the output power. Power loss is given by
PLOSS = PIN - POUT
I OUT 1( RMS) = I OUT1 x 1 +
r 12
(5)
where r is the inductor ripple current r VOUT1 x (1 - D)/(IOUT1 x L x fSW)
(2a) (2b)
(6)
or
PLOSS = POUT (1- )/
where: L is the inductance. fSW is the switching frequency. D is the duty cycle. D = VOUT1/VIN1 (7)
Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and all the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor and, from this, use Equation 3 to calculate the power dissipation in the ADP5033 buck converter. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, and the power lost on each LDO can be calculated using Equation 12. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equation 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the two LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDO provided by Equation 12.
ADP5033 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the P-MOSFET and the N-MOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by PCOND = [RDSON-P x D + RDSON-N x (1 - D)] x IOUT12 (9) where RDSON-P is approximately 0.2 , and RDSON-N is approximately 0.16 at 125C junction temperature and VIN1 = VIN2 = 3.6 V. At VIN1 = VIN2 = 2.3 V, these values change to 0.31 and 0.21 , respectively, and at VIN1 = VIN2 = 5.5 V, the values are 0.16 and 0.14 , respectively.
Rev. 0 | Page 15 of 28
ADP5033
Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) x VIN12 x fSW where: CGATE-P is the P-MOSFET gate capacitance. CGATE-N is the N-MOSFET gate capacitance. For the ADP5033, the total of (CGATE-P + CGATE-N) is approximately 150 pF. The transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by PTRAN = VIN1 x IOUT1 x (tRISE + tFALL) x fSW (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW. For the ADP5033, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. (10)
JUNCTION TEMPERATURE
The total power dissipation in the ADP5033 simplifies to PD = PDBUCK + PDLDO1 + PDLDO2 (13) In cases where the board temperature TA is known, the thermal resistance parameter, JA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD x JA) (14) The typical JA value for the 16-ball, 0.5 mm pitch WLCSP is 57C/W (see Table 6). A very important factor to consider is that JA is based on a 4-layer 4 in x 3 in, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper used to remove the heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. The exposed pad should be connected to the ground plane with several vias. If the case temperature can be measured, the junction temperature is calculated by TJ = TC + (PD x JB) where TC is the case temperature and JB is the junction-toboard thermal resistance provided in Table 6. When designing an application for a particular ambient temperature range, calculate the expected ADP5033 power dissipation (PD) due to the losses of all channels by using the Equation 8 to Equation 13. From this power calculation, the junction temperature, TJ, can be estimated using Equation 14. The reliable operation of the converter and the two LDO regulators can be achieved only if the estimated die junction temperature of the ADP5033 (Equation 14) is less than 125C. Reliability and mean time between failures (MTBF) is highly affected by increasing the junction temperature. Additional information about product reliability can be found in the ADI Reliability Handbook, which can be found at www.analog.com/reliability_handbook. (15)
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by PDLDO = [(VIN - VOUT) x ILOAD] + (VIN x IGND) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small, and it can be ignored. (12)
Rev. 0 | Page 16 of 28
ADP5033 THEORY OF OPERATION
VOUT1 VOUT2 VDDA PWM COMP VIN1 ILIMIT PSM COMP PWM/ PSM CONTROL BUCK1 PSM COMP PWM/ PSM CONTROL BUCK2 SOFT START SOFT START ILIMIT GM ERROR AMP ENBK1 75 75 ENBK2 GM ERROR AMP PWM COMP VIN2
ADP5033
LOW CURRENT SW1
LOW CURRENT SW2
OSCILLATOR DRIVER AND ANTISHOOT THROUGH SYSTEM UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN
DRIVER AND ANTISHOOT THROUGH
OPMODE SEL B Y A MODE2
PGND2 ENLDO1 600 MODE
PGND1
ENA ENABLE AND MODE CONTROL ENB
ENBK1 ENBK2 ENLDO1 ENLDO2 VDDA
LDO UNDERVOLTAGE LOCK OUT R1 LDO CONTROL
LDO UNDERVOLTAGE LOCK OUT R3 LDO CONTROL
VDDA R2 600
ENLDO1
R4
09788-003
VIN3
AGND VOUT3
VIN4
VOUT4
Figure 43. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5033 is a micropower management unit (PMU) combing two step-down (buck) dc-to-dc convertors and two low dropout linear regulators (LDO). The high switching frequency and tiny 16-ball WLCSP package allow for a small power management solution. To combine these high performance regulators into the PMU, there is a system controller allowing them to operate together. The buck regulators can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the buck switching frequency is always constant and does not change with the load current. If the MODE pin is at logic low, the switching regulators operate in auto PWM/PSM mode. In this mode, the regulators operate at fixed PWM frequency when the load current is above the power saving current threshold. When the load current falls below the power save current threshold, the regulator in question enters PSM where the switching occurs in bursts. The burst repetition is a
function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. The auto PWM/PSM mode transition is controlled independently for each buck regulator. The two bucks operate synchronized to each other. When a regulator is turned on, the output voltage ramp is controlled through a soft start circuit to avoid a large inrush current due to the charging of the output capacitors.
Thermal Protection
In the event that the junction temperature rises above 150C, the thermal shutdown circuit turns off all the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20C hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temperature drops below 130C. When coming out of thermal shutdown, all regulators restart with soft start control.
Rev. 0 | Page 17 of 28
ADP5033
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the system. If the input voltage on VIN1 drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on VIN1 rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for USB applications. For these models, the device reaches the turn-off threshold when the input supply drops to 3.65 V typical. In case of a thermal or UVLO event, the active pull-downs (if factory enabled) are enabled to discharge the output capacitors quickly. The pull-downs remain engaged until the input supply voltage or thermal fault event is no longer present.
BUCK1 AND BUCK2
The two bucks use a fixed frequency and high speed current mode architecture. The bucks operate with an input voltage of 2.3 V to 5.5 V.
Control Scheme
The bucks operate with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency but shift to a PSM control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency.
Enable/Shutdown
The ADP5033 has two enable pins (ENA and ENB). A high level applied to the enable pins enables a certain selection of regulators defined by factory programming. For example, the ADP5033 can be factory programmed to enable BUCK1 and LDO2 with ENA and BUCK2 and LDO1 with ENB. When both enables are low, all regulators are turned off. When both enable pins are high, all regulators are turned on. All possible regulator combinations can be factory programmed to operate with the ENA and ENB pins. Figure 44 shows the regulator activation timings for the ADP5033 when both enables are connected to VINx. Figure 44 also shows the active pull-down activation.
VIN1
PWM Mode
In PWM mode, the bucks operate at a fixed frequency of 3 MHz set by an internal oscillator. At the start of each oscillator cycle, the pFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pFET switch and turns on the nFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold.
VUVLO VPOR
VOUT1
VOUT3
VOUT4
30s (MIN) VOUT2 50s (MIN)
30s (MIN) 50s (MIN)
BUCK1, LDO1, LDO2 PULL-DOWNS BUCK2 PULL-DOWN
Figure 44. Regulators Sequencing on the ADP5033 (ENx = VINx)
Rev. 0 | Page 18 of 28
09788-148
ADP5033
PSM
The bucks smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When either of the bucks enters PSM, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold. The ADP5033 has a dedicated MODE pin controlling the PSM and PWM operation. A high logic level applied to the MODE pin forces both bucks to operate in PWM mode. A logic level low sets the bucks to operate in auto PSM/PWM.
Current Limit
Each buck has protection circuitry to limit the amount of positive current flowing through the pFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load.
100% Duty Operation
With a dropin input voltage or with an increase in load current, the buck may reach a limit where, even with the pFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the pFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage.
PSM Current Threshold
The PSM current threshold is set to100 mA. The bucks employ a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from the PSM. The PSM current threshold is optimized for excellent efficiency over all load currents.
Active Pull-Downs
All regulators have optional, factory programmable, active pulldown resistors discharging the respective output capacitors when the regulators are disabled by the ENx pins or by a faulty condition. The pull-down resistors are connected between VOUTx and AGND. Active pull-downs are disabled when the regulators are turned on. The typical value of the pull-down resistor is 600 for the LDOs and 75 for the bucks. Figure 44 shows the activation timings for the active pull-down during regulator activation and deactivation.
Oscillator/Phasing of Inductor Switching
The ADP5033 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Additionally, the ADP5033 ensures that when both bucks are in PWM mode, they operate out of phase, whereby the Buck2 pFET starts conducting exactly half a clock period after the Buck1 pFET starts conducting.
LDO1 AND LDO2
The ADP5033 contains two LDOs with low quiescent current and two low dropout linear regulators and provides up to 300 mA of output current. Drawing a low 25 A quiescent current (typical) at no load makes the LDO ideal for batteryoperated portable equipment. Each LDO operates with an input voltage of 1.7 V to 5.5 V. The wide operating range makes these LDOs suitable for cascading configurations where the LDO supply voltage is provided from one of the buck regulators. Each LDO also provides high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with just a small 1 F ceramic input and output capacitor. LDO1 is optimized to supply analog circuits because it offers better noise performance compared to LDO2. LDO1 should be used in applications where noise performance is critical.
Short-Circuit Protection
The bucks include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current.
Soft Start
The bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter.
Rev. 0 | Page 19 of 28
ADP5033 APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 1.
Output Capacitor
Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT x (1 - TEMPCO) x (1 - TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.24 F at 1.8 V, as shown in Figure 45. Substituting these values in the equation yields CEFF = 9.24 F x (1 - 0.15) x (1 - 0.1) = 7.074 F To guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
12
Inductor
The high switching frequency of the ADP5033 bucks allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 H and 3 H. Suggested inductors are shown in Table 8. The peak-to-peak inductor current ripple is calculated using the following equation:
I RIPPLE = VOUT x (VIN - VOUT ) VIN x f SW x L
where: fSW is the switching frequency. L is the inductor value. The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation:
I PEAK = I LOAD( MAX ) + I RIPPLE 2
Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI.
Table 8. Suggested 1.0 H Inductors
Vendor Murata Murata Taiyo Yuden Coilcraft(R) TDK Coilcraft Toko Model LQM2MPN1R0NG0B LQM18FN1R0M00B BRC1608T1R0M EPL2014-102ML GLFR1608T1R0M-LR 0603LS-102 MDT2520-CN Dimensions (mm) 2.0 x 1.6 x 0.9 1.6 x 0.8 x 0.8 1.6 x 0.8 x 0.8 2.0 x 2.0 x 1.4 1.6 x 0.8 x 0.8 1.8 x 1.69 x 1.1 2.5 x 2.0 x 1.2 ISAT (mA) 1400 150 520 900 230 400 1350 DCR (m) 85 26 180 59 80 81 85
10
CAPACITANCE (F)
8
6
4
2
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
Figure 45. Typical Capacitor Performance
Rev. 0 | Page 20 of 28
09788-004
0
ADP5033
The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: VRIPPLE = I RIPPLE V IN = (2 x f SW ) x 2 x L x C OUT 8 x f SW x C OUT The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 F and a maximum of 40 F. The buck regulators require 10 F output capacitors to guarantee stability and response to rapid load variations and to transition into and out of the PWM/PSM modes. In certain applications, where one or both buck regulators power a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 F to 4.7 F because the regulator does not expect a large load variation when working in PSM mode (see Figure 47).
Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation:
ESRCOUT VRIPPLE I RIPPLE
Table 9. Suggested 10 F Capacitors
Vendor Murata Taiyo Yuden TDK Panasonic Type X5R X5R X5R X5R Model GRM188R60J106 JMK107BJ475 C1608JB0J106K ECJ1VB0J106M Case Size 0603 0603 0603 0603 Voltage Rating (V) 6.3 6.3 6.3 6.3
Rev. 0 | Page 21 of 28
ADP5033
Input Capacitor
Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 46 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating.
1.2
I CIN I LOAD( MAX )
VOUT (VIN - VOUT ) VIN
To minimize supply noise, place the input capacitor as close to the VINx pin of the buck as possible. As with the output capacitor, a low ESR capacitor is recommended. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 F and a maximum of 10 F. A list of suggested capacitors is shown in Table 10.
Table 10. Suggested 4.7 F Capacitors
Vendor Murata Taiyo Yuden Panasonic Type X5R X5R X5R Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M Case Size 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3
1.0
CAPACITANCE (F)
0.8
0.6
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5033 LDOs are designed for operation with small, space-saving ceramic capacitors, but function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure the stability of the ADP5033. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5033 to large changes in load current.
0.4
0.2
0
1
2 3 4 DC BIAS VOLTAGE (V)
5
6
Figure 46. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage: CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V, as shown in Figure 46. Substituting these values into the following equation, CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5033, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
Input Bypass Capacitor
Connecting a 1 F capacitor from VIN3 and VIN4 to ground reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or a high source impedance is encountered. If greater than 1 F of output capacitance is required, increase the input capacitor to match it.
Table 11. Suggested 1.0 F Capacitors
Vendor Murata TDK Panasonic Taiyo Yuden Type X5R X5R X5R X5R Model GRM155B30J105K C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F Case Size 0402 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3 10.0
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5033 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a
Rev. 0 | Page 22 of 28
09788-006
0
ADP5033 PCB LAYOUT GUIDELINES
Poor layout can affect ADP5033 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines:
* * *
*
Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference.
*
Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Connect VIN1 and VIN2 together close to the IC using short tracks.
Rev. 0 | Page 23 of 28
ADP5033 TYPICAL APPLICATION SCHEMATIC
ADP5033
VIN1 C1 4.7F ALWAYS ON ENA ON OFF VIN: 2.3V TO 5.5V ACT ENB VIN2 C2 4.7F SW2 VOUT2 PGND2 FROM VIO (1.7V MIN) VIN3 C3 1F VIN4 C4 1F C6 4.7F
BK1 BK2 LD1 LD2
SW1 VOUT1
L1 1H
VCORE
PROCESSOR
VCORE
BUCK1
PGND1
C5 4.7F
MODE VIO L2 1H
GPIO
VIO
BUCK2
ANALOG SUBSYSTEM VANA
LDO1
VOUT3 C7 1F
FROM VCORE (1.7V MIN)
LDO2
AGND
VOUT4 C8 1F
VDIG
09788-152
Figure 47. Processor System Power Management with PSM/PWM Control
Rev. 0 | Page 24 of 28
ADP5033 OUTLINE DIMENSIONS
2.12 2.08 SQ 2.04 0.660 0.602 0.544 0.022 REF SEATING PLANE
4 3 2 1 A
BALL 1 IDENTIFIER 0.330 0.310 0.290 1.50 REF
B C D
TOP VIEW
(BALL SIDE DOWN)
0.380 0.352 0.324
0.04 NOM COPLANARITY 0.280 0.250 0.220
0.50 REF BOTTOM VIEW
(BALL SIDE UP)
Figure 48. 16-Ball Wafer Level Chip Scale Package [WLCSP] Back-Coating Included (CB-16-7) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADP5033ACBZ-1-R7 Temperature Range -40C to +125C Output Voltage (V) 2 VOUT1: 1.2 V VOUT2: 3.3 V VOUT3: 2.8 V VOUT4: 1.8 V Options
UVLO: 2.25 V Pull-Downs on All Channels
ENA Controlled Channels 3 BUCK2, LDO1
Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board
Package Option CB-16-7
013009-B
Branding Code LHX
ADP5033-1-EVALZ
1 2
Z = RoHS Compliant Part.
For additional options, contact a local sales or distribution representative. Additional options available are
BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.82 V, 1.8 V, 1.6 V, 1.5 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V. LDO1 and LDO2: 3.3 V, 3.0 V, 2.9 V, 2.8 V, 2.775 V, 2.5 V, 2.0 V, 1.875 V, 1.8 V, 1.75 V, 1.7 V, 1.65 V, 1.6 V, 1.55 V, 1.5 V, 1.2 V. UVLO: 2.25 V or 3.9 V. Active pull-down: Yes/No. 3 ENA activated channels (ENB controls the other channels).
Rev. 0 | Page 25 of 28
ADP5033 NOTES
Rev. 0 | Page 26 of 28
ADP5033 NOTES
Rev. 0 | Page 27 of 28
ADP5033 NOTES
(c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09788-0-5/11(0)
Rev. 0 | Page 28 of 28

▲Up To Search▲

Price & Availability of ADP5033

	To Download ADP5033 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .